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agula's avatar
agula
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

PCIe SR-IOV Arria 10 Configuration Space

Hi All, Is the configuration space handled completely by the IP, or does the memory for the configuration space exist in your application logic memory. For example, is it in the user-space bar log...
BoonT_Intel's avatar
BoonT_Intel
Icon for Frequent Contributor rankFrequent Contributor
5 years ago

Hello Sir,

For MSI-X, you will need to configure the parameters in the IP GUI as below:

IP Settings -> Interrupt capabilities -> PF0 (VF) MSI-X

And this parameters is map to the Figure 46 “MSI-X Capability Registers” as describe in the UG- https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10_pcie_sriov.pdf#page=82

So, from the host (driver), you will need read these MSI-X capabilities register to check the table and PBA offset.