Forum Discussion
DChak3
New Contributor
6 years agoPCie_ptile config read no response from ptile
In our setup (avery bfm with other qsys design (includes hard ips) for the very first pcie config read no response from pcie_ptile hard IP. How can we identify whether ptile is timed out or not. I...
SengKok_L_Intel
Regular Contributor
6 years agoHi,
Is this problem happen during enumeration? Are you using the example design in Appendix D (page 211)?
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_ptile_pcie_avst.pdf