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Arintel's avatar
Arintel
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5 years ago

PCIe-MM-DMA: Read/Write DMA & BAR0/2 mutually exclusive?

Hi All, I'm using the Intel PCIe-MM-DMA IP core. In my design, I would often need to schedule a Write-DMA to transfer data from the FPGA to the host system memory. However, sometimes, when there's ...
BoonT_Intel's avatar
BoonT_Intel
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5 years ago

Hi,

Just want to understand the problem that you are facing is write-DMA left pending for a long time. Or you are unable to perform the other activity before the write-DMA complete.

If the first one, then may I know how long it left pending? I guess maybe this is due to the FC setting.

If the second one, then I think it is expected behaviour. We need to wait for the write-DMA to complete before we can perform other operation.


  • Arintel's avatar
    Arintel
    Icon for New Contributor rankNew Contributor
    5 years ago

    Hi,

    Thank you for your reply.

    It's the second case where I'm unable to perform the other activity before the write-DMA complete.

    Is this a limitation of PCIe in general? Or is it possible to customize the IP Core's Descriptor Controller (when generated externally) to allow concurrent Read/Write-DMA and BAR0/2 activities?

    Thanks,

    Ari