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EastGun-A's avatar
EastGun-A
Icon for New Contributor rankNew Contributor
3 years ago
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PCIe Memory write TAG

hello, i wonder about the pcie protocol. i just know memory write request don't need completion. then, why tag bit is essential?? is any function in memory write request??? tag bit do the orderi...
  • Wincent_Altera's avatar
    Wincent_Altera
    3 years ago

    Hi,

    Based on my understand the answer is No, there is no additional function specifically for correcting the order with tag bits when applying relaxed ordering in a posted write request. The purpose of relaxed ordering is to allow certain reordering of memory operations for improved performance, but it does not involve any specific mechanism to correct the order with tag bits. If you require a specific ordering of memory operations, you should use a different memory ordering model or synchronization techniques such as fences or barriers. Please correct me if you feel I am wrong.

    Regards,

    Wincent_Intel

EastGun-A's avatar
EastGun-A
Icon for New Contributor rankNew Contributor
3 years ago

Thank you so much for taking the time for me.

In addition, in the avalon streaming interface, the payload limit is 512B and the read request limit is 4096B. Then, is the completion with data created by automatically splitting the TLP into multiple pieces in the P-tile? (I wonder if the address is automatically changed and the TLP is created.)

Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,

In the Avalon streaming interface, the payload limit refers to the maximum size of a single data payload that can be transferred in one transaction, which is 512 bytes. The read request limit, on the other hand, specifies the maximum size of a read request, which is 4096 bytes.

If a read request exceeds the payload limit, it needs to be divided into multiple transactions. This division and subsequent reassembly of the data is typically handled by the Avalon interface itself, or by the hardware or software components connected to it. The address may be automatically adjusted for each transaction to retrieve the appropriate data, and multiple Transaction Layer Packets (TLPs) may be generated to transfer the complete data.

The specific implementation details may vary depending on the design and configuration of the system using the Avalon interface, but the interface itself provides mechanisms to handle larger requests by splitting them into multiple transactions as necessary.

Hope this answered your question.

Regards,
Wincent_Intel