Forum Discussion
New ContributorPCIe Memory write TAG
Hi,
Based on my understand the answer is No, there is no additional function specifically for correcting the order with tag bits when applying relaxed ordering in a posted write request. The purpose of relaxed ordering is to allow certain reordering of memory operations for improved performance, but it does not involve any specific mechanism to correct the order with tag bits. If you require a specific ordering of memory operations, you should use a different memory ordering model or synchronization techniques such as fences or barriers. Please correct me if you feel I am wrong.
Regards,Wincent_Intel
Regular ContributorHi
The tag bit in a posted memory write generally does not affect the behavior or outcome of the write operation itself. The tag bit is typically used for tracking and identifying specific memory regions or access types, but it does not directly impact the actual write operation.
Changing the tag bit for a posted memory write may be possible depending on the system and the specific implementation of the memory controller. However, it is important to note that altering the tag bit arbitrarily could potentially disrupt the memory system's intended behavior and could lead to unpredictable results or errors.
Regards,
Wincent_Intel
EastGun-AThank you so much for taking the time for me.
In addition, in the avalon streaming interface, the payload limit is 512B and the read request limit is 4096B. Then, is the completion with data created by automatically splitting the TLP into multiple pieces in the P-tile? (I wonder if the address is automatically changed and the TLP is created.)
- Wincent_Altera
Hi,
In the Avalon streaming interface, the payload limit refers to the maximum size of a single data payload that can be transferred in one transaction, which is 512 bytes. The read request limit, on the other hand, specifies the maximum size of a read request, which is 4096 bytes.
If a read request exceeds the payload limit, it needs to be divided into multiple transactions. This division and subsequent reassembly of the data is typically handled by the Avalon interface itself, or by the hardware or software components connected to it. The address may be automatically adjusted for each transaction to retrieve the appropriate data, and multiple Transaction Layer Packets (TLPs) may be generated to transfer the complete data.
The specific implementation details may vary depending on the design and configuration of the system using the Avalon interface, but the interface itself provides mechanisms to handle larger requests by splitting them into multiple transactions as necessary.
Hope this answered your question.
Regards,
Wincent_Intel
