Forum Discussion
New ContributorPCIe Memory write TAG
Hi,
Based on my understand the answer is No, there is no additional function specifically for correcting the order with tag bits when applying relaxed ordering in a posted write request. The purpose of relaxed ordering is to allow certain reordering of memory operations for improved performance, but it does not involve any specific mechanism to correct the order with tag bits. If you require a specific ordering of memory operations, you should use a different memory ordering model or synchronization techniques such as fences or barriers. Please correct me if you feel I am wrong.
Regards,Wincent_Intel
Regular ContributorHi,
For the tag bit information, I found one article.
It may answer all of your question.
second question.
PCIe ordering rules ensure that all memory transactions, including continuous write requests, are executed in a predictable and reliable manner. The PCIe ordering rules specify how read and write operations should be ordered in time and how they should interact with other transactions on the bus.
For continuous write requests, PCIe ordering guarantees that the data is written to the target memory in the order in which it was sent by the initiator. This is achieved through a combination of various mechanisms such as the Memory Write and Invalidate (MWI) command and the Non-Posted Write (NPW) protocol.
In NPW protocol, the data is written to the target memory without waiting for any acknowledgement from the receiver. The receiver, in turn, sends an acknowledgement once the write operation is complete. The MWI command is used to invalidate the cache lines in the memory hierarchy of the receiving device so that the updated data can be fetched from memory.
Overall, the PCIe ordering rules ensure that all transactions on the bus are executed in the order in which they were issued, regardless of the type of operation or the devices involved. This ensures that continuous write requests are processed in a reliable and predictable manner, without any loss or corruption of data.
Hope this answered your question. let me know if further clarification is needed.
Regards,
Wincent_Intel
EastGun-AThank you so much for your reply.
Then, in the case of posted memory write, does it matter what the tag bit is?
I wonder if it is possible to arbitrarily change the tag bit for posted memory write.
