PCIe Inbound Byte write data corruption ... SolutionID rd04172014_563

Thanks Skbeh,

I have modified the design to support Gen3 X1 and 64 bit TXS port.

I am passing Inbound byte write operations , without DWORD corruption at the host now.

I am passing Inbound byte read operations , without NIOS II hanging.

This is on an emulator that only runs Gen1 rates but with the 128 bit TXS design, we previously failed the byte write / read operations.

I am fairly confident that when trained to Gen3 X1 I will get the same passing results with this design point.

Gen3 X1 may be sufficient for the exerciser I have else I can investigate the 256 bit design point.

Thanks, Bob.