PCIe Hard IP Issues With EFI

I have a fpga design using the Intel Hard IP for PCIe on the Intel Cyclone 10GX development board. The design works well when using traditional BIOS booting, but I'm seeing a very large number of Avalon MM bus issues when booting with EFI. Reads from fpga registers often return trash in the EFI case. Any ideas what the problem may be?

Quartus 22.1 Pro. I've also tried Quartus 21.4 and have the same issue. In both the traditional BIOS and EFI cases I'm seeing the physical address of the PCIe card being mapped in the 32bit address space of the PC host. The PC host is an Intel PC running 64 bit Linux. Same FPGA image in both cases.