PCIe hard IP endpoint with hpg_ctrler signal

Hi,

I'm using QuartusII 13.0.0.156, and have instantiated a PCIe 4x Hard IP block in endpoint mode for a CycloneIV.

The generated VHDL includes a "hpg_ctrler" port, which, according to the documentation and common sense, should not exist in endpoint mode. Am I missing something obvious here?

Simon