Forum Discussion

andrecap's avatar
andrecap
Icon for New Contributor rankNew Contributor
5 years ago

PCIe Hard IP Cyclone 10 peer to peer communication

Hi, we are trying to achieve communication between two endpoint FPGAs. The architecture of the system is as follows: PC (root complex) ...
BoonT_Intel's avatar
BoonT_Intel
Icon for Frequent Contributor rankFrequent Contributor
5 years ago

Hello Sir,

If you can see the data come out from the FPGA1, then usually the issue is due to the driver of the host. As you can see from this article, the p2p transaction is very dependent on the host.

https://www.kernel.org/doc/html/latest/driver-api/pci/p2pdma.html

and you can follow the recommendation to amend the host driver accordingly.


andrecap's avatar
andrecap
Icon for New Contributor rankNew Contributor
5 years ago

Hello Mr. BoonT,

thanks for your rapid response.

I looked at the documentation, but that kind of discussion seems to be referring to the case where it's the host that is using the DMA controller (dmaengine in linux for something like that).

In our case, we are instead using the DMA controller inside one of the FPGA to orchestrate the transaction (for example, fpgaA). I should have specified better.

We followed the documentation at this link to implement the DMA transfer (chap. 6.7.4):

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10_pcie_avmm_dma.pdf

Do you have any other suggestion?

Kind Regards,

Andrea