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FFULC's avatar
FFULC
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5 years ago

PCIe Hard IP core in Cyclone V GX

I am using a Cyclone 5CGXFC5C7F23C8N in a new design and planning to implement a PCIe x4 endpoint with CvP enabled. The CVP user guide, UG-01101, states that I need to use the bottom left hard IP w...
FFULC's avatar
FFULC
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5 years ago

Hi John

I have shown you the screenshot before but can I use REFCLK1 as an alternative PCIe clk? REF_CLK comes on to our board through a backplane from the Root Complex. If we have signal integrity issues then I'd like to connect a local 100Mhz LVDS clock to REFCLK1. Will this work?

Thanks

Frank

JohnT_Altera's avatar
JohnT_Altera
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,

If you are using the bottom Transceiver then you can only use REFCLK0.