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FFULC's avatar
FFULC
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5 years ago

PCIe Hard IP core in Cyclone V GX

I am using a Cyclone 5CGXFC5C7F23C8N in a new design and planning to implement a PCIe x4 endpoint with CvP enabled. The CVP user guide, UG-01101, states that I need to use the bottom left hard IP w...
JohnT_Altera's avatar
JohnT_Altera
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5 years ago

Hi,


If you would like to simplified the board then you can directly use the JTAG connection from the FPGA to configure the EPCQ-L flash device. You can use any blaster to programmed it using JIC file (You can use factory default SFL or implement SFL into your design).


You can use any EPCQ flash device as when you are performing CvP, the required file size is very small (IOCSR size only). Please refer to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-v/cv_51002.pdf Table 65 for the filesize of the bitstream.



  • FFULC's avatar
    FFULC
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    5 years ago

    Thanks John

    As I am using a C5 part, I will use a EPCQ128A flash device in AS x4 mode.

    Maybe this is too large ? But that is what Table 65 states