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FFULC's avatar
FFULC
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5 years ago

PCIe Hard IP core in Cyclone V GX

I am using a Cyclone 5CGXFC5C7F23C8N in a new design and planning to implement a PCIe x4 endpoint with CvP enabled. The CVP user guide, UG-01101, states that I need to use the bottom left hard IP w...
JohnT_Altera's avatar
JohnT_Altera
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5 years ago

Hi,


The transceiver pin looks good to me. You will need to use nPERSTL1 pin as this is the use for CvP.


FFULC's avatar
FFULC
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5 years ago

Thank you John.

I am now looking at what config scheme is best for me alongside CvP.

I am planning to use AS x4 with a EPCQ device for the periphery image for my Cyclone V GX, as below:

I have 2 questions:

What is the best way to program the EPCQ? I want to use the ByteBlaster interface, do I need to connect it to the AS interface rather than to the Cyclone's JTAG pins (via SFL bridge) when using CvP?

Also what size EPCQ part can I use?