Forum Discussion

FFULC's avatar
FFULC
Icon for New Contributor rankNew Contributor
5 years ago

PCIe Hard IP core in Cyclone V GX

I am using a Cyclone 5CGXFC5C7F23C8N in a new design and planning to implement a PCIe x4 endpoint with CvP enabled. The CVP user guide, UG-01101, states that I need to use the bottom left hard IP w...
  • FFULC's avatar
    FFULC
    Icon for New Contributor rankNew Contributor
    5 years ago

    Thanks John, I have connected as shown below. Using Ch3 in L1 as the 4th lane. Is this correct?

    Also, should I use nPERSTL0 or L1 ?

    Many Thanks

    Frank