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Altera_Forum's avatar
Altera_Forum
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14 years ago

PCIe bus master random access to all host memory

I'm not sure if the PCI Express MegaCore hard IP can do what I want. I'll describe what I'm trying to achieve. I'd like to set up a bus-master scatter-gather DMA between on-device memory and a ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Hi all,

- I am already having a design that communicates with x86 processor from NIOS II using the shared memory over the PCIe interface.

- With new design my aim would be to reverse the shared memory and place it on the x86 processor DDR memory instead of FPGA SSRAM.

- And aware of this would require some complex address translation logic to be included in the fabric.

- I came to know that, "txs" signal in the PCIe interface ip core will access the host memory, but I want to know how that signal will access DDR memory or some other internal memory on x86 processor.

- Also I like to know how DDR memory in x86 processor is used?

- I am interested to know if someone has already achieved something similar and if it is possible to get hold of a reference design for this or related configuration to start with.