PCIe bus master random access to all host memory

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I'd like to set up a bus-master scatter-gather DMA between on-device memory and a host memory buffer. The host memory buffer is contiguous in virtual address space,

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I'm not sure how this fits in with the Avalon-MM-to-PCI Express address translation table.<...>

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That's perfectly possible.

You do not need any (BAR) translation table on the FPGA, because the FPGA is doing SGDMA directly to/from host memory, so there is no BAR access involved.

For a ready to go SGDMA solution with drivers, see http://www.lancero-pcie.com/

Best regards,

Leon Woestenberg