PCI Express help

Hi Paul,

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The example will not compile for me however. I am getting error "SystemVerilog error at qsys-top.sv(267) : can't resolve implicit port connection(s) to instance ""u4" without a module declaration or an extern equivalent" and I have followed all the instructions carefully on that PDF on how to create the PCIe end-point.

This design example is for Stratix IV and I am trying to compile for Stratix V. Is that the issue here?

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Most likely. You need to look at the top-level component generated by the Qsys system. The ports on that component instance need to match whatever is instantiated in the top-level design.

I suspect that the PCIe interface ports changed slightly between the Stratix IV and V, and you simply need to correct for those differences.

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We seem to have hit a brick wall here and are struggling to get an example working on Stratix V. There are plenty of documents showing how to use QSys to generate the PCIe hard IP for Stratix V but not on how to use it.

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The wall you have hit now is really just understanding how to debug HDL code. Open up Qsys and look at the "HDL Example" it produces, and then check that the ports match the instance.

Cheers,

Dave