PCI Express help

Thanks Dave,

I've managed to add the components now. The example will not compile for me however. I am getting error "SystemVerilog error at qsys-top.sv(267) : can't resolve implicit port connection(s) to instance ""u4" without a module declaration or an extern equivalent" and I have followed all the instructions carefully on that PDF on how to create the PCIe end-point.

This design example is for Stratix IV and I am trying to compile for Stratix V. Is that the issue here?

We seem to have hit a brick wall here and are struggling to get an example working on Stratix V. There are plenty of documents showing how to use QSys to generate the PCIe hard IP for Stratix V but not on how to use it.

Cheers,

Paul