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Braveheart83's avatar
Braveheart83
Icon for New Contributor rankNew Contributor
6 years ago

PCI Express Hard IP Avalon-MM legacy interrupt handling

Hello I would like to interrupt a PCI express root port from inside the FPGA through Avalon-MM bridge as an endpoint. Internally a level based interupt signal is generated that should generate an ...
BoonT_Intel's avatar
BoonT_Intel
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

Hi Sir,

I believe the interrupt that you talking here is the MSI/MSIX?

For PCIe, MSI is transmitted as posted memory write, so no completer is needed. Thus, application just assume the RP side already taken care the interrupt unless RP return NAK.

For second question regarding the pulse width, I believe your concern is since there is to acknowledgment from RP about the interrupt, then how long you should hold it. Answer is yes, 62.5MHz pulse is ok as long as there is rising edge.