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JD0's avatar
JD0
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4 years ago

PCI express Arria II GX problem

Hello, I want to communicate between 2 FPGA (root port and endpoint) on PCIe ver.1.1 with x1 link. I use Quartus 13.1. I have downloaded Design Example - PCIe Rootport Examples from https:...
JD0's avatar
JD0
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4 years ago

In my final FPGA design for Arrria II GX (EP2AGX65) I need to use 2 instances of PCIe Core (because of our dual-star backplane topology), and Arria II GX has only one HARD IP PCIe.

So, it would be better to find final solution for SOFT IP PCIe Cores, and not one solution for HARD IP and another for SOFT IP.

When it is possible to have Avalon-MM interface in HARD IP, why is not possible to have it in SOFT IP? Really Intel does not have any component, that translate PCIe TLP´s packets from Avalon-ST interface into Avalon-MM interface? How does it make in HARD IP, it has to be similar. In the HARD IP does the solution exist, how is it done there?

skbeh's avatar
skbeh
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4 years ago

There is no embedded component/bridge that can support pcie avst-to-avalon_mm conversion.

Arria II GX is a legacy device and the avmm interface support in rootport mode/soft IP is limited.