Forum Discussion
Gyud0
Occasional Contributor
Occasional ContributorParallel Flash Loader IP - mapping ports problem
hey, I was creating the Parallel Flash Loader IP by Quartus MegaFunction. I integrated this IP in the Top design file( add the IP's ports, declare the IP, mapping the IP to the Top's port). Then I ...
NurAiman_M_Intel
Super Contributor
Super ContributorHi,
Thank you for contacting Intel community.
Have you refer to Intel PFL guideline below:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_pfl.pdf
Let me know if you need further information.
Regards,
Aiman
Gyud0Hey,
in this guide I see that the PFL not support active-parallel configuration (only passive-serial and fast-passive-parrallel). Can you suggest me a way to configure the FPGA by Active parallel?
THX,
