NIOS II simulation issue - design is not loading. Need information to load the design correctly.

Trying to simulate a NIOSII processor with an Avalon to AXI bridge connected to a third party IP. Getting the error "(vopt-2133) Instantiating 'cpu_pcie_master_avalon_if' has exceeded the recursion depth limit of 200." The system is generated in Qsys. Quartus Prime Pro 17.1 is the version used. What could be the issue?