Forum Discussion
Altera_Forum
Honored Contributor
9 years agoDear,
In my model the ROM was data input and DRAM was data output. It didn't have explicit inputs and outputs. When It was compiled It was only created two inputs: clock and areset, but any output. Please, don't ask me about why I did it. I have changed my model and now it is more professional, have better interface with outside world. Thank you all.