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I was wondering any means of converting the software implementation to an HDL RTL design and comparing the performances.
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http://en.wikipedia.org/wiki/c_to_hdl It looks like today there is some free options (NISC,
c-to-verilog.com, ROCCC, ...) as well as big name commercial (Mentor) to choose from. As far as Altera's offering goes, I think the situation is that it "works" it is just not being further developed. If you are willing to jump through some hoops with current releases in order to use it, you can.
I understand this is not where you are aiming, but once you wrap your hands around using tools like this, it seems like a useful topic of for a paper/wiki might be a brief summary with 2013 view point of the output you get from variety of tools using your standard well-known RSA math as the test case. I think the challenge would be making any of them understand that you are working with 1024-bit operands and not arrays of 32-bit words, for example.
Here is one relatively current paper (obviously, biased toward one tool):
http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=5474060 You may get additional / more useful feedback from this forum with a new thread with different topic soliciting opinions, since there may be people with relevant first hand knowledge of current offerings.
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