Oh sorry, I think I misunderstood the question. So you've always been able to get the design working with one of the xaui interface, but you run into problems when you have two or more interfaces? Are they running off the same refclk? You will need to dump both into their own dual clock fifos, but then you read out of them (or write to them) with a common clock from one of the xaui interfaces (after letting them fill up a couple cycles to account for any phase difference). That being said, I'm not familiar with the Stratix V and XAUI soft IP. Depending on your design, you could also keep them on their own separate clock domains.
Cheers