Forum Discussion

Jasvinder's avatar
Jasvinder
Icon for New Contributor rankNew Contributor
5 years ago

Multi Channel DMA future multiple queue support

Hi all, I am looking to implement PCIe hard IP to transfer data from an FPGA device to a host in the future, I have done a similar thing previously using Xilinx IP components that allow use of many...
BoonT_Intel's avatar
BoonT_Intel
Icon for Frequent Contributor rankFrequent Contributor
5 years ago

Hi Sir,

Yes, seem like the IP is designed feasible to enable the multi-channel for AVST. However, there is no plan to enable it in any future version yet. I guess the reason is there is no marketing request for this feature. If you want to make this happen in future for usage, please contact sales representative in your region.