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EDing
New Contributor
New ContributorMSGDMA and Hard Memory Controller Interface
There is an issue with our MSGDMA and Hard Memory Controller interface. We are using the MSGDMA to read from DDR Memory via the Hard Memory Controller. In the attached snapshot from Signal Tap,...
NurAida_A_Intel
Frequent Contributor
Frequent ContributorHi EDing,
May I know what are the setting used in the Frame Buffer? Can you share the setting applied if you don't mind?
And do u turn on Frame Writer mode?
If you turn off the Frame Writer mode in your setting, then Bit 31 is invalid but you can perform both read and write to DDR IP . If this setting is turn on , then the Available bit is valid but you can only perform read to DDR IP.
What I can see here is you want to perform read and write to DDR, by right this Frame Writer mode need to turn off .
Thanks
Regards,
NAli1
