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Altera_Forum
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11 years ago

Modular SGDMA - Streaming to Memory Mapped Random first write.

Hi, I am using the Modular SGDMA to write memory into DDR3 memory, and then a second one to read it back out again. The reading is all working fine and writing into the memory works as well, ex...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

I've been probing in signalTap and modelsim the signals directly at the SGDMA block. They seem both the same where it matters (i.e. there are don't cares in the simulation which have some value in signaltap).

It seems that the problem is when the MLAB cells for the 'fifo with byte enable' block have their ena signal high, but their portabyteenamasks signal low, for some reason the contents gets written to 0xFFFFFFFF. But the same cells for a second SGDMA controller in the design (MM->ST one) are the same MLAB type, but work fine.