Modify Ariia V ALTLVDS_TX data rate during work

Thank you for the quick reply!

Just to clarify something. I'm thinking of using a "master PLL" to generate 2 clocks : 162 MHz and 270 MHz for the logic blocks.

those 2 clocks will go through ALTCLKCTRL and only one will act as the system clock .

1.Can I use this clock as reference clock of the ALTLVDS PLL? (which in turn will produce x10 serial clock)

2.What do you mean "high-speed serial I/O" ? (is it an IP i can instantiate )

Thanks again