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Altera_Forum's avatar
Altera_Forum
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13 years ago

Memory Mapped Slave interface in Qsys lacks associated reset

I have a simple DSP Builder project that includes an Avalon Memory Mapped Slave block from the standard blockset. In SOPC Builder I can import systems with Avalon-MM slave blocks without any problem, but in Qsys I get an error message stating that the "Interface must have an associated reset." Is the block incompatible with Qsys, or is there some extra hoop I forgot to jump through? In the worst case I could write my own Avalon interface in Verilog, but I'd rather use the built-in library block if possible.

I'm using Quartus II 11.0, SP 0.01. If this has been fixed in a more recent version of the tools please advise.

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    --- Quote Start ---

    Refer to page 13 of http://www.altera.com/literature/manual/mnl_avalon_spec.pdf

    In short, every interface must have a signal that provides the reset. Reset is a required input.

    Kevin Jennings

    --- Quote End ---

    To me that is meaningless response. I have exactly the same problem. I am exporting a standard Avalon Interface using QSYS from a daughter Qsys module to parent Qsys module. Yet, I get the error that the Interface must have an associated reset. Ok, we know that. Without getting into writing a wrapper for a standard interface how do I do associate a reset (and a clock) with the Interface?

    When I look at the daughter Qsys module on its own, the interface has an associated clock and reset. The association is not being transferred to the parent.

    So how to do it? Thanks for any help.
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    You need to export the clk and reset signals from the daughter qsys system. Once you do that, it will show it on the parent system.