Forum Discussion
Altera_Forum
Honored Contributor
10 years agoThanky you for your answer. Actually i am trying to send 16 bit data through FPGA to PC. For that i am using a shift register and FIFO before data proceed to ethernet megacore function. There are some files generated from the ethernet megacore function including a instantiate file. If i instantiate my shift register and fifo module inside the ethernet instantiation file is that okay or am i doing anything wrong? Appreciate your kind advice. Thanks