Forum Discussion
Occasional ContributorMAX 10 flash controller wrapping mode - non-functional
Hi,
From the SIgnalTap, I observed that you only provide read signal for 1 clock cycle when you are using burst count of 2. I would recommend you to provide read signal at least 2 clock cycle when you are using burstcount of 2 in wrapping mode.
Please refer to Figure 18 in https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_ufm.pdf
Regular ContributorHi,
Could you share with me your IP setting and maybe your Quartus design?
Occasional ContributorHi John.
Thanks. Here is my flash_controller that wraps the intel flash ip. I've also included the flash ip itself so you can see the settings that I'm using, along with how I applied the knowledge base patch I mentioned above. That patch seems to still be required in Quartus 20.1.1, although I do see changes to the ip since the Quartus 19.1 version.
I have several clients who can read-write and I process them in round robin fashion. The two clocks are because I run the flash controller at 2x my system clock to get fast access.
If you use the controller to debug, set one of the addr inputs, leave request high, write_n high, addr_config low. Supply a clock and that should be enough.
Would be great to be able to use the lower level access at altera_onchip_flash_block directly if there is documentation on this.
Thanks,
Mark
- foft
Here is a very minimal project to illustrate the problem.
Extract the tar and run ./build.sh to build two identical examples.
I didn't use any external pins and used the internal oscillator to ease running on your max10.
- foft
I should note identical examples except for burst or incremental mode. Incremental mode works but burst mode does not.
There is a signaltap included in order to inspect the results.
