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ymiler's avatar
ymiler
Icon for Contributor rankContributor
5 years ago
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LVDS SERDES

Hi, I have IP serdes in my FPGA (FPGA A) - This SERDES have connection with another FPGA (other board - FPGA B) According to my project requirements - I should inject(output) and get(input) ...
  • AminT_Intel's avatar
    AminT_Intel
    5 years ago

    Hello,

    Thanks for the details. Output clock at FPGA A can be placed at any LVDS pair pins and input clock at FPGA B should be sufficient.

    Thank you.

ymiler's avatar
ymiler
Icon for Contributor rankContributor
5 years ago

I drew a little VISIO that describe my design :

My problem is : Unlock / Lock indication is depend by FPGA loading

I wonder if the root cause is pin location -

My question is : Should I place both clocks (in & out ) in the dedicated pin clocks or maybe I should do it only for the input clock ?

Note : I dont have the option to locate input & output to SERDES pin dedicated clocks ( because board planning)

Thanks

AminT_Intel's avatar
AminT_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hello,

Thanks for the details. Output clock at FPGA A can be placed at any LVDS pair pins and input clock at FPGA B should be sufficient.

Thank you.

  • AminT_Intel's avatar
    AminT_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users

    • AminT_Intel's avatar
      AminT_Intel
      Icon for Regular Contributor rankRegular Contributor
      5 years ago

      Otherwise, the community users will continue to help you on this thread. Thank you.