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ZaidSahawneh
New Contributor
New ContributorLow Latency 10 G Ethernet on Stratix 10 SX dev kit
Hello, I am trying to run the 10G LL Ethernet example design on a Stratix 10 SX dev kit board. The protocol is out of reset. Signal Tap reports the tx and rx paths to be ready. I am tryi...
paveetirrasrie_Altera
Frequent Contributor
Frequent ContributorHello ZaidSahawneh,
Apologies for delayed response.
Have you tried running through design example tcl script using system console?
You may follow the procedure in UG below:
https://www.intel.com/content/www/us/en/docs/programmable/683026/23-4-22-0-4/procedure-71370.html
Regards,
Pavee
