Low Latency 10 G Ethernet on Stratix 10 SX dev kit

I realized I had the CSR signals were pulled up to the top level primary input/output from an early experiment when by default they are wired to 0s in the instantiation of altera_eth_10g_mac_base_r within altera_eth_top. I returned them to the default set up and the results changed minimally. The show_stats.tcl output reports the following attached.

How should I be addressing these signals? There is already a JTAG to AVMM module in the example design but I'm not sure how to access it via System Console (new to the tool) to perform my own reads and writes and the intel scripts are a bit confusing to ingest and repurpose.