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JFK's avatar
JFK
Icon for New Contributor rankNew Contributor
4 years ago

Low Frequency Phase Lock Loop

Could anyone use a Low Frequency Multiplying Phase Locked Loop IP designed for use in FPGA and CPLDs with these specs: 1. Instant lock 2. Small foot print 3. 2ns lock to leading edge 4. 1...
Ash_R_Altera's avatar
Ash_R_Altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

Thanks for the document. I see that this might be a gap in the industry. May be in future someone will implement the invention proposed in the document.

As of now, there is no solution in Intel FPGAs.

Usually low frequency signals are handled by divider circuits or oversampling them using higher frequency clocks.


Regards