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JFK's avatar
JFK
Icon for New Contributor rankNew Contributor
4 years ago

Low Frequency Phase Lock Loop

Could anyone use a Low Frequency Multiplying Phase Locked Loop IP designed for use in FPGA and CPLDs with these specs: 1. Instant lock 2. Small foot print 3. 2ns lock to leading edge 4. 1...
Ash_R_Intel's avatar
Ash_R_Intel
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,

There is no such PLL in the Intel FPGA portfolio. Most of the PLLs require a minimum of 5MHz input clock. Lock time varies and a minimum value is not published. The max time to lock is generally 1ms for many of Intel FPGA devices.


Regards