Forum Discussion
JFK
New Contributor
New ContributorLow Frequency Phase Lock Loop
Could anyone use a Low Frequency Multiplying Phase Locked Loop IP designed for use in FPGA and CPLDs with these specs:
1. Instant lock
2. Small foot print
3. 2ns lock to leading edge
4. 1...
Ash_R_Altera
Regular Contributor
Regular ContributorHi,
There is no such PLL in the Intel FPGA portfolio. Most of the PLLs require a minimum of 5MHz input clock. Lock time varies and a minimum value is not published. The max time to lock is generally 1ms for many of Intel FPGA devices.
Regards
