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New Contributor

7 years ago

LL 10G Eth MAC AVST TX Interface Timing Diagram

10G LL Ethernet MAC: Newbie question on the timing diagram for the AVST TX Interface. In TX introduction, the user guide says: "The MAC TX receives the client payload data with the destination and s...

Deshi_Intel

Regular Contributor

7 years ago

Hi JShel4,

Short answer to your question 1 is YES.

I presume you are using Intel Arria 10 FPGA. I think the best way to help you is refer to an existing reference design. The reference design will show you how to configure MAC IP register and also have example on how to generate Ethernet frame packet to MAC IP.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-20016.pdf

Thanks.

Regards,

dlim

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LL 10G Eth MAC AVST TX Interface Timing Diagram

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