Forum Discussion

Amirg's avatar
Amirg
Icon for New Contributor rankNew Contributor
5 years ago

Jesd204b interface seems to misbehave after upgrading quartus from 16 to 19

Hi, i have a design with jesd204b interfacing adc device, but after upgrading to quartus 19.2, the sync signals seems to assert and deassert all the time. i re-generated all of the ip's. what coul...
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,

Thanks for your update. From the latest signaltap, I can see that there is no anomaly with the CDR. It is still maintaining lock-to-data mode through the sync_n toggling. I have had discussion with Factory on this and this observation seems to be something new to them.

Just would like to check with you on the following:

1. Just wonder if you have IPS access? As per discussion with Factory, they think that it would be great if we can continue to work this out through IPS.

2. If you does not have IPS access, probably you can engage with your local FAE to assist you to open a case.

3. Can you share with me the actual signaltap file? I would like to zoom in further to see if there is any anomaly on the data received to see if can spot any anomaly.

4. Just would like to check with you if this observation (16.2 pass, 19.2 fail) occurs across all boards or only specific board?

5. Just would like to check with you if this observation can be consistently replicated in the failing board?

Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin