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ONors's avatar
ONors
Icon for New Contributor rankNew Contributor
5 years ago

JESD204B debug

I have a custom board which uses JESD204B to receive samples from a ADC. I have two such boards. On one of them JESD204B works as expected, on the other it does not. On the board that is not working ...
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


Thanks for your update. Would you mind to share me the signaltap files? I am not familiar with analyzing the VCD files.


One debug test that you can look into to further narrow down the problem location is creating a duplex JESD instance, enable the serial loopback, send data from TX to RX and see if RX is able to achieve link up. This could help to isolate if it is within FPGA or ADC related.


Thank you.


ONors's avatar
ONors
Icon for New Contributor rankNew Contributor
5 years ago

Here is the stp-file with logged data from both the failing and the working board.