Occasional Contributor
ContributorHi David
The suggestion would be generate the JESD204B design example. Refer to the design example for the connection between transport layer and IP core.
Choose the closest allowable parameter values for generation. Modify the post-generated design parameters manually in the Quartus software to match your desire parameter settings.
The generated JESD design example has a transport_layer folder with 4 RTL files.
1) For information about the path data remapping in the Transport Layer.
Refer to https://www.intel.com/content/www/us/en/docs/programmable/683094/22-1/design-example-user-guide.html
For example Table 19, case M=4, S=1 where F=2, F2_FRAMECLK_DIV=2, user have to reorder the samples at application layer so it inputs correct data format to the transport layer and then generate expected Data Out as indicated in table below.
The data mapping in Table 19 jesd204_tx_datain[127:0]:
jesd204_tx_datain[127:0] = {{F14F15, F10F11,F6F7, F2F3}, {F12F13, F8F9,F4F5, F0F1}}
is equivalent to
jesd204_tx_datain[127:0] = {{M3S0, M2S0,M1S0, M0S0}, {M3S0, M2S0,M1S0, M0S0}}
2) Refer to section 'Customizing the Design Example' on page 50 of below user guide for more information about customizing the design example.
JESD204B Intel® Arria 10 FPGA IP Design Example User Guide
https://www.intel.com/content/www/us/en/docs/programmable/683113/
