Will,
Since you are using AN832, I believe you are using Stratix 10 device. Could you confirm you are using Stratix 10.
Being locked-to-data only indicates that your Receiver is receiving data at the desired frequency (or data rate). It does not mean you are receiving the correct data in the timing order that is required. Please refer to JESD IP user guide (section 4.2.1 onwards) on what type of data you should be receiving to transition to different phases from CGS to ILAS to user mode.
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_jesd204b.pdf
Please check by probing the mentioned signals using signaltap to help resolves your data_align = 0 issue.
If you need further help related to debugging the data_align issue, please capture the following status signals in signaltap and attach the .stp file.
-jesd204_rx_dataout
-jesd204_rx_data_valid
-jesd204_rx_data_ready
-jesd204_rx_link_data_ready
-jesd204_rx_link_error
- rx_dev_sync_n
- jesd204_rx_int
- dev_lane_aligned
- rx_somf
-jesd204_rx_pcs_data
-jesd204_rx_pcs_data_valid
-jesd204_rx_pcs_kchar_data
-jesd204_rx_pcs_errdetect
-jesd204_rx_pcs_disperr
Since you are using a supported LMF configuration, I am not suspecting your issue to be caused by changing the LMF configuration.
As for the RX_INTERRUPT = 1, please check your AVS related clock frequency and the reset as described in section 4.5 of the user guide.
Please let me know if you checked everything listed above and still cannot zoom in. Also, it will be halpful it you could attach signaltap snapshots on FPGA or register readback in system console showing the failures reported. This will enable me to more effectively help you debug your issue.
Regards,
Nathan
Occasional Contributor
