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Is it possible to use a common external reference clock for L lanes transceivers in JESD 204 IP core??or do we need separate external reference clock for each sets of lane??
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Did you look at the JESD204B standard?
http://www.jedec.org/sites/default/files/docs/jesd204b.pdf (You have to register, but the standard is free)
The links are encoded, so in general you could create a system with reference oscillators, and allow the clock-and-data recovery unit to track any phase/frequency-shifts between those oscillators, just as you would in a network setup. However, if you are using multiple ADCs, and those ADCs are synchronous, then its just as easy to use a common reference clock for all the ADCs and FPGAs.
Analog Devices has an article on JESD204B
http://www.analog.com/static/imported-files/tech_articles/jesd204b-survival-guide.pdf What are you trying to do?
Cheers,
Dave
Honored Contributor
