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Ajas's avatar
Ajas
Icon for New Contributor rankNew Contributor
5 years ago

Issue in Avalon MM clock crossing bridge

Hi, I am using Avalon MM clock crossing bridge interconnect to connect between 125Mhz clock master and 100 MHz slave. Slave has asserted waitrequest to 1'b1. However, the IP on the master side out...
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
5 years ago

(Host = master, agent = slave; assuming m0 here is the host and s0 is an agent)

Can you post a picture of your system design? It's not clear what the connections are here. Indeed, waitrequest (which is a host input, not an output) is being held high by the interconnect, which prevents the host from issuing any further commands. If the agent is not issuing waitrequest, as seen in your sim, that means the interconnect is issuing the waitrequest, perhaps due to arbitration or some other factor. Seeing the system design would help understand what's going on.

Ajas's avatar
Ajas
Icon for New Contributor rankNew Contributor
5 years ago

Thank you for the response.

The interconnect is consuming the request from master. It has FIFO depth = 2 for command fifo. when more than 2 requests are raised, the waitrequest is asserted to the master. It is found by running more transaction in the simulation.

Understood the issue, thank you for the support.

Thanks,

Asan.