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SSmit7's avatar
SSmit7
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6 years ago

Is the channel indicator byte (0x7C) in the SPI IP Core guaranteed?

I have implemented the SPI to Avalon-MM IP core in my MAX10 design. While running stress tests on the data transfer between a processor and the MAX10, there is a very rare situation where the channel...
Rahul_S_Intel1's avatar
Rahul_S_Intel1
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

Hi SSmit,

Is it possible to share sample project where we can create the issue , I have consulted the software team , they have the below request .

Sample project

Signal tap of the signals

SSmit7's avatar
SSmit7
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6 years ago

Hi RSree

I am able to send you the Qsys project to test, but I may not send you the rest of the project. I have no SignalTap signals to show you, we detected the error in on the receiver side, which is the SPI port of a NXP T1042 processor. Where can I send the qsys projects?