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SSmit7
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6 years ago

Is the channel indicator byte (0x7C) in the SPI IP Core guaranteed?

I have implemented the SPI to Avalon-MM IP core in my MAX10 design. While running stress tests on the data transfer between a processor and the MAX10, there is a very rare situation where the channel...
SSmit7's avatar
SSmit7
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6 years ago

Hi Sree

The problem is not with the SPI protocol itself. The SPI protocol layer appears to be working as intended. The problem is that the encoding used by Altera is not behaving consistently. This means that the error is probably occurring on the Packet layer of the SPI Core. If you refer to original question, you will see that I did not mention the problem of extra bits, as this is not what is occuring. The issue is that we are receiving an Idle character (0x4A) when we are supposed to receive a Channel Indicator character (0x7C). I provided an example of the behaviour. Please can you inform the internal guys about that.