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SSmit7
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6 years ago

Is the channel indicator byte (0x7C) in the SPI IP Core guaranteed?

I have implemented the SPI to Avalon-MM IP core in my MAX10 design. While running stress tests on the data transfer between a processor and the MAX10, there is a very rare situation where the channel...
SSmit7's avatar
SSmit7
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6 years ago

Hi there

I'm not sure what you are asking. The power utilised by the FPGA is not very high, though there are a few other pins driving signals. I am not sure how this will affect the SPI though? Are you suggesting that this could be a power consumption issue?