Forum Discussion
SSmit7
New Contributor
New ContributorIs the channel indicator byte (0x7C) in the SPI IP Core guaranteed?
I have implemented the SPI to Avalon-MM IP core in my MAX10 design. While running stress tests on the data transfer between a processor and the MAX10, there is a very rare situation where the channel...
Rahul_S_Intel1
Frequent Contributor
Frequent ContributorHi ,
I cannot say like that , can you try the same in ideal condition , that mean to say only usign spi prorotocl , and power utilized by the fpga is minimum
