mnazemiNew Contributor6 years agoIs it possible to skip the generation of cosimulation support in the Intel HLS Compiler? I was wondering if it is possible to only generate Verilog files.
Recent DiscussionsRX Mac segmented interface detailed informationFIT Rate for 5M570ZT144I5Nquartus ram gen full HDLAgilex 5 Reset Sequencer - Design Assitant reports IPC-40038 violationTriple-Speed Ethernet IP for Agilex 5 fails during Quartus Synthesis