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MZama2's avatar
MZama2
Icon for New Contributor rankNew Contributor
6 years ago

Is it possible to monitor LTSSM signals on TEST_OUT bus for PCIe Hard IP?

Hi guys, I was wondering if it is possible to monitor LTSSM signals on TEST_OUT bus. I am using a Cyclone IV GX Transceiver starter kit provided by Altera and have parametrized a PCIe Hard IP in Q...
BoonT_Intel's avatar
BoonT_Intel
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

Hi,

I am sorry to said that CIV is a legacy device and we do not have details information about it. What I say here is follow the document, the test_out is for pipe status signal and my understand is these signal is used for internal debug previously. If you want to know the LTSSM, I will suggest you monitor the LTSSM signal directly.